1. Field of the Invention
This invention relates generally to the field of sub-circuits used to synchronize the energizing of the various parts of an extended circuit. Such a subcircuit is characterized as a "power-up circuit," and serves to delay the application of electrical power at power-up until the level of voltage available is high enough to ensure the proper operation of the circuit. More particularly, it is a circuit that delays the application of power to the output pullup and pulldown stages in output buffers until those stages can be controlled by the rest of the output buffer and associated circuitry. More particularly yet, the present invention provides a means of delaying circuit activation until the rising power-supply-voltage is sufficiently high to ensure that the output buffer is placed in a definite state before its pullup and pulldown stages are energized. Yet more particularly, the present invention introduces a hysteresis into the energizing/de-energizing process such that the turn-on-threshold-voltage marking the point at which power supply voltage is applied to the extended circuit as the power supply voltage is rising, is significantly higher than the turn-off-threshold-voltage marking the point at which power supply voltage is removed from the extended circuit as the power supply voltage is falling. This ensures that a relatively high turn-on-threshold-voltage can be set, without a concern that the circuit will be de-energized by normal fluctuations in the applied power supply voltage.
Another sub-field in which the circuit of the present invention can be categorized is that of reset circuits, i.e., circuits used to set to logic-low the levels of a group of logic stages in an extended circuit or, more generally, to set the levels of the logic stages to definite values, logic-low or logic-high.
2. Description of the Prior Art
In general, power is supplied to an extended logic circuit by a power supply connected across the circuit. This usually is accomplished by connecting the low-potential power rail of the logic circuit to ground and connecting the high-potential power rail to the output of the power supply. The high-potential power rail voltage is usually referred to as V.sub.cc, and the low-potential power rail as GND. Normally the power supply is part of the circuitry and when ac power is provided to the power supply the output voltage of that power supply will not instantaneously increase to the full design voltage for the high-potential power rail of the logic circuit. Rather, the voltage output of the power supply, V.sub.ps, will commence at ground level and ramp up more or less linearly to the design voltage over a period on the order of milliseconds. Problems arise because long before V.sub.ps brings the high-potential power rail up to the level where the entire circuit is operating properly, the circuit will become active. This can result in various stages being placed in indeterminate states, as opposed to being in one of the two well-defined binary states. This in turn can result in excess power dissipation both within the circuit and from the common bus to which the circuit is ultimately coupled.
In general, each three-state output buffer connected to a common bus will be regulated by an output enable gate which can place the buffer in its disabled (high-Z) state regardless of the other signals to the buffer. This provides a direct way to ensure that the buffers are all disabled during the potentially disruptive period during which the power supply voltage is ramping up. A signal from a power-up circuit is simply coupled to the output enable gate of each buffer, a power-up circuit designed to provide a disabling signal through that output enable gate during the period of ramp-up. That is, a power-up circuit is used which will generate at an early stage in the ramping up of V.sub.ps a signal which can be used to hold the output buffer disabled. In other words, the power-up circuit is a "fix" added to the main circuit to make up for the fact that the main circuit cannot generate a disabling signal soon enough. The power-up circuit will generate an output voltage V.sub.PU which is in a definite logic state by the time that V.sub.ps reaches the level at which any parts of the extended logic circuit can start conducting. That definite-logic-state signal can then be used to ensure that the output logic buffer is disabled. A generic array incorporating a power-up circuit is depicted in FIG. 1, which shows the output enable gate (OEG) to be an OR gate with one input from the power-up circuit and one input from that part of the circuit which is supposed to generate the output enabling signal once the circuit is in operation and that particular buffer is supposed to be active. With the layout of FIG. 1, it can be seen that the output of the power-up circuit, V.sub.PU, must be logic-high throughout that part of the V.sub.ps ramp-up for which the buffer is vulnerable. For transistor-transistor logic (TTL), this will be the range from about 2V.sub.BE to 4V.sub.BE, with V.sub.BE being defined as the voltage drop across the base/emitter junction of a conducting bipolar transistor (i.e., the bias required to cause forward current across that pn junction). Thus the requirement is that the power-up circuit put out a logic-high signal while V.sub.ps is varying from 2V.sub.BE to 4V.sub.BE during ramp-up, and that it then be locked at logic low so as to return control of the buffer to nOE. Although this has been stated in relation to the specific schematic circuit of FIG. 1, it can be seen that the main requirement is that the power-up circuit coupled into the circuit to be protected must somehow generate a well-defined binary signal during the period of vulnerability during which the rest of the circuit, if left unguarded, could generate a series of mixed states, neither logic high nor logic low.
Early power-up circuits are described in Houk et al. (U.S. Pat. 4,481,430, issued 1984) and in Kantz (U.S. Pat. 5,051,611, issued in 1991). The basic circuit of Houk is shown in FIG. 2 (Prior Art). It can be seen that as V.sub.ps, ramps up from ground, the power-up output voltage V.sub.PU will first follow V.sub.ps, since there will be no current through resistor R3 and hence no voltage drop across that resistor. At some point on that ramp-up--depending on the way in which the power-up circuit is coupled to the rest of the circuit, and in particular to the output enable gate--the output buffer will be disabled. Although the exact voltage at which that happens can only be determined from a consideration of the specifics of that coupling, it is easy to determine the value of V.sub.p, for which the power-up circuit yields control. It is when transistor Q1 turns on. Transistor Q1 will be non-conducting until V.sub.ps is high enough to cause forward conduction through diodes D1 and D2 and hence provide base drive to Q1. Even after both diodes D1 and D2 are conducting, Q1 will not conduct until the drop across R2 equals V.sub.BE, the voltage required across the base-emitter junction of Q1 to turn on the transistor. The "forward" base-emitter voltage drop will be taken to be the same across all transistors, and also to be the forward-conduction voltage drop for all the circuit diodes (which are generally bipolar transistors themselves with the collector and base nodes tied together). Thus it can be seen that Q1 will turn on when V.sub.ps reaches a voltage V.sub.BE [3 +R1/R2], or about 4V.sub.BE when the R1 and R2 resistors are comparable to one another. When Q1 turns on the output of the power-up circuit will fall to V.sub.sat (the collector-emitter drop across a conducting bipolar transistor of the circuit) and will remain there as long as V.sub.ps remains above V.sub.BE [3+R1/R2]. For this duration, V.sub.PU will be locked at logic-low. The gate to which V.sub.PU is connected--generally an OR gate as shown in FIG. 1--is wired so that a logiclow V.sub.PU does not have any effect on the state of the output buffer. It can be seen, then, that for V.sub.ps &gt;V.sub.BE [3+R1/R2] the power-up circuit cuts out (cedes control of the buffer). The problem with the invention of Houk et al. is that it does not allow for fluctuations in the high-potential power rail voltage which fluctuations, though large, are not inconsistent with proper operation of the circuit. These fluctuations will occur for a number of reasons and are a normal feature of a properly-functioning circuit. In particular, fluctuations in the high-potential power rail voltage which brings that voltage as low as 4V.sub.BE above ground are not inconsistent with proper functioning of the circuit; nevertheless, the power-up circuit of Houk et al. will shut down the circuit when such a fluctuation occurs.
The circuit of Kantz addresses the susceptibility of earlier power-up circuits to shut down circuits in the presence of normal operational V.sub.ps fluctuations. It does this by introducing a hysteresis such that, once the power-up circuit has relinquished control over the extended circuit at the V.sub.ps threshold V.sub.UTh, it will not reassert control until V.sub.ps has fallen below a different threshold V.sub.DTh, where V.sub.DTh &lt;V.sub.UTh. FIG. 3 depicts the essence of the power-up circuit of Kantz. As V.sub.ps increases from ground potential the diode stack is at first not conducting; transistor Q3 receives no base drive and hence is non-conducting. The output voltage of the power-up circuit is equal to V.sub.ps during this interval, as with that of Houk et al. and, like that of Houk et al. will cause the buffer to be disabled once a certain value for V.sub.ps --typically around 2V.sub.BE -is reached. Note that once V.sub.ps exceeds V.sub.BE, transistor Q2 turns on. However, the output voltage V.sub.PU continues to track V.sub.ps, since the base current through Q2 will result in negligible voltage drop across resistor R7. There will, however, be current through R4, and a corresponding voltage drop across R4 with Q2 conducting. Initially, this current all passes through Q2. When V.sub.ps reaches a certain voltage, however, the diode stack consisting of D3 and D4 will start conducting and the current through R4 will then be the sum of the respective currents through the diode stack branch and through Q2. As V.sub.ps continues to increase, it will pass the threshold V.sub.UTh at which base drive is supplied to Q3; at this point, V.sub.PU will drop to V.sub.SAT, turning Q2 off. The threshold V.sub.UTh is the point at which the power-up circuit of Kantz yields control over the buffer. The turning off of Q2 at V.sub.UTh is essential to the hysteresis effect in Kantz. Now all of the current through R4 passes through the diode stack. Consequently, when V.sub.ps decreases-either during power-down or during a transitory fluctuation-it can reach a voltage V.sub.DTh lower than V.sub.UTh before the base voltage of Q3 falls below V.sub.BE causing Q3 to turn off and hence the power-up circuit to shut down the output buffer. Because Kantz allows the power-up threshold voltage V.sub.UTh to be set higher than the power-down threshold voltage V.sub.DTh, it permits V.sub.UTh to be set higher than would be desirable when one has to select a single threshold which is to be a compromise between (1) providing adequate protection during power-up and (2) avoiding shutdowns for minor fluctuations in the power supply voltage.
Although the power-up circuit of Kantz allows separation of the threshold voltages V.sub.UTh and V.sub.DTh, it is limited with regard to the fixing of the values of those threshold voltages by means other than selection of alternative resistance values. This is of particular concern given the types of variations observed in fabricated resistors, wherein actual resistance values can deviate by as much as 30% from design values. Any alternative means used to change V.sub.UTh and V.sub.DTh, such as by adding supplemental diode means to the circuit branch including transistor Q2 could bring the power-up circuit outside the range of acceptable operating conditions, particularly as required power supply levels are reduced. What is therefore needed is a simple bipolar power-up circuit with hysteresis.